1. Field of the Invention
The present invention relates to a semiconductor package testing apparatus, and more particularly, to a semiconductor package testing apparatus and a multilevel pusher thereof, for performing an electrical characteristic test on semiconductor packages.
2. Description of the Related Art
Semiconductor chips separated from a wafer after a wafer process can be manufactured into a semiconductor package by an assembling step. Subsequently, various tests are performed to check the reliability of the semiconductor package, as well as products resulting from the formation of the package.
A general test includes an electrical characteristic test that tests electrical characteristics and defects of semiconductor chips, and a burn-in test that determines the integrity of semiconductor chips and defects occurring thereof under severe conditions, for example, when an abnormally high temperature, voltage, current, etc. is applied, as compared to a normal operating condition.
The electrical characteristic test checks for either a normal operation or short-circuit state in a semiconductor chip by bringing all input/output terminals of the semiconductor chip into contact with a test circuit substrate on which a test signal generating circuit is adapted. In the electrical characteristic test of a semiconductor package, a handler is mainly used, for example, a conventional semiconductor package testing apparatus including a handler disclosed in U.S. Pat. No. 7,232,328, incorporated herein by reference in its entirety.
A semiconductor package testing apparatus is described as follows, referring to the drawings.
FIG. 1 is a sectional view schematically showing a semiconductor package testing apparatus according to conventional art.
As illustrated in FIG. 1, in a conventional semiconductor package testing apparatus, a test substrate 10 includes a test circuit, and further includes a socket 40 that is electrically coupled between the test substrate 10 and a semiconductor package 2. The test substrate 10 is positioned in a lower part of an insert block 17. The semiconductor package 2 is inserted into an insert hole of the insert block 17, and the semiconductor package is compressed by a pusher 30.
The semiconductor package 2 is electrically coupled with the test circuit through a plurality of socket terminals 44 formed in a center of the socket 40. A socket guide 41 for protecting the socket 40 surrounds the socket 40. Guide pins 32 of the pusher 30 are inserted into guide holes 20 of the insert block 17 and guide bushes 411 of the socket guide 41. In both edge parts of the socket guide 41, guide bushes 411 are formed into which guide pins 32 of the pusher 30 extending from the insert block 17 are inserted.
Thus, the insert block 17 is positioned in the periphery part above the socket 40 supported on the test circuit, and the semiconductor package 2 can be inserted into the insert hole of the insert block 17. The semiconductor package 2 is compressed by an operation in which the pusher 30 above the insert block 17 is lowered in a z-direction. In this manner, the pusher 30, the insert block 17, and the socket 40 can be aligned mutually.
At this time, when the semiconductor package 2 is inserted into the insert block 17, the semiconductor package 2 must be compressed to a predefined level. Thus, when the pusher 30 is lowered to the predefined level, or below, a contact area between a terminal of the semiconductor package 2 and the socket terminal 44 is reduced, and so reliability of electrical characteristic test decreases. Further, when the pusher 30 is lowered more than the predefined level, the socket terminal 44 may be damaged. For example, the pusher 30 can lower the semiconductor package 2 about 0.25 mm to about 0.30 mm.
Further, in the conventional semiconductor package testing apparatus, a lowered level of the pusher 30 is limited to testing a semiconductor package 2 having a specific, single thickness. Thus, operation of the pusher is limited to testing packages of that thickness.